DDR3L 4Gb智慧传输::热点频道::大联大控股





• Density: 4Gbits
• Organization
- 32M words x 16 bits x 8 banks (for 256x16)
- 64M words x 8 bits x 8 banks (for 512x8)
• Package size:
- 96-ball FBGA (9x13.5mm for 256x16)
- 78-ball FBGA (9x10.6mm for 512x8)
- Lead-free (RoHS compliant) and Halogen-free
• Power supply: 1.35V (Typ)
- VDD, VDDQ = 1.283V to 1.45V
- Backward compatible for VDD, VDDQ=1.5V ± 0.075V
• Data rate:
- 1866Mbps/1600Mbps/1333Mbps/1066Mbps (max.)
• Operating temperature: –25°C to +95°C / Storage temperature: –55°C to +100°C
• Double-data-rate architecture: two data transfers per clock cycle
• The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture
• Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver
• DQS is edge-aligned with data for READs; center- aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK transitions
• Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS
• Data mask (DM) for write data
• Posted /CAS by programmable additive latency for better command and data bus efficiency
• On-Die Termination (ODT) for better signal quality 
- Synchronous / Dynamic / Asynchronous ODT
• Multi Purpose Register (MPR) for pre-defined pattern read out
• ZQ calibration for DQ drive and ODT
• Programmable Partial Array Self-Refresh (PASR)
• /RESET pin for Power-up sequence and reset function
• SRT range: - Normal/extended
• Programmable Output driver impedance control




Kingston推出的嵌入式DDR3L产品,符合目前市场上主流的on-board DRAM for embedded产品应用。金士顿DDR3L目前采用Elpida 2xnm制程,并且符合JEDEC DDR3/DDR3L 的标转规范,Kingston DDR3L for low-vltage,容量为4Gb,除了当DDR3L (1.35V for lower power comsumption)使用,也可当作一般DDR3(1.5V± 0.075V)使用,与市售主流DDR3/DDR3L皆可Pin2Pin,采用FBGA封装78-ball & 96-ball。