SoC Processor for Automotive Infotainment DRA756车联网::热点频道::大联大控股


SoC Processor for Automotive Infotainment DRA756



‧Architecture Designed for Infotainment Applications
‧Full-HD Video (1920 × 1080p, 60 fps) – Multiple Video Input and Video Output – 2D and 3D Graphics
‧ ARM® Dual Cortex®-A15 Microprocessor Subsystem
‧Up to two C66x™ Floating-Point VLIW DS
‧Up to 2.5MB of On-Chip L3 RAM
‧Two ARM® Dual Cortex®-M4 Image Processing Units (IPUs)
‧Up to Two Embedded Vision Engines (EVEs)
‧Video Processing Engine (VPE)


‧Human-Machine Interface (HMI)
‧Digital and Analog Radio
‧Rear Seat Entertainment
‧Multimedia Playback
‧Web Browsing
‧ADAS Integration


DRA75x and DRA74x (Jacinto 6) infotainment applications processors are built to meet the intense processing needs of the modern infotainment-enabled automobile experiences.
The device enables Original-Equipment Manufacturers (OEMs) and Original-Design Manufacturers (ODMs) to quickly implement innovative connectivity technologies, speech recognition, audio streaming, and more. Jacinto 6 devices bring high processing performance through the maximum flexibility of a fully integrated mixed processor solution. The devices also combine programmable video processing with a highly integrated peripheral set.
Programmability is provided by dual-core ARM Cortex-A15 RISC CPUs with Neon™ extension, TI C66x VLIW floating-point DSP core, and Vision AccelerationPac (with one or more EVEs). The ARM allows developers to keep control functions separate from other algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software.
Additionally, TI provides a complete set of development tools for the ARM, DSP, and EVE coprocessor, including C compilers and a debugging interface for visibility into source code.
The DRA75x and DRA74x Jacinto 6 processor family is qualified according to the AEC-Q100 standard.