代理產線

Server Memory Interface Chipsets

 2016-01-06

【基本資料】

【產品特性】

DDR4 PRODUCTS are:

Register
‧ Used in both RDIMM and LRDIMM
‧ Paired with 4DB0124 for LRDIMM
‧ 32-bit 1:2 command/address register
‧ 1.2 V Vdd operation
‧ Supports up to 4 packages ranks and 8 logical ranks with native 3DS support
‧ Advanced I/O enable control
‧ Support at-speed BCOM bus for data buffer control
‧ Automatic impedance calibration
‧ New DDR4 power saving protocols
‧ Command/ Address Parity Checking
‧ Control register RCW readback
‧ 1 MHz I2C bus

Data Buffer
‧ Paired with 4RCD0124 for LRDIMM
‧ Dual 4-bit bidirectional data registers with differential data strobes
‧ 1.2 V Vdd operation
‧ Automatic impedance calibration
‧ BCOM Parity Checking
‧ Control register BCW readback

Temp Sensor + EEPROM
‧ Used in UDIMM, RDIMM, LRDIMM
‧ Temperature accuracy up to ±0.5°C
‧ 512 byte EEPROM for vendor info
‧ 1 MHz I2C bus

BENEFITS:
‧ All devices are JEDECR compliant and meet stringent requirements for reliability and application compliance
‧ Up to 35% DDR4 power savings compared to DDR3
‧ Enables Terabyte DIMM memories
‧ Parity and CRC for improved data error recovery
‧ Improved debug and system margining

【產品應用】

Applications requiring deeper memory at higher data rates and lowest power including enterprise Servers, data centers, workstations, storage devices, and communications.

【文字介紹】

IDT’s DDR4 Registered Clock Driver, Data Buffer and Temp Sensor make up the industry’s first complete chipset for DDR4 registered dual in-line memory modules (RDIMMs) and load reduced dual in line memory modules (LRDIMMs). With DDR4 data rates climbing to 3.2 Gb/s and higher, the clear advantages afforded by RDIMM and LRDIMM as a speed-scalable memory technology are expected to drive adoption across a broad array of memory-intensive computing and storage applications.

Through flexible I/O control, timing and voltage calibration, and control register programmability, the IDT DDR4 Registered Clock Driver (4RCD0124) and Data Buffer (4DB0124) enable faster data rates at higher densities on all JEDECR defined DDR4 LRDIMM and RDIMM topologies. DIMM topology configuration and DRAM information is stored in IDT’s Temperature Sensor EEPROM (TSE2004).

With a deep knowledge of memory interface chipsets based on successful chipset introductions for all DDR generations, IDT’s devices will provide reliable performance for your application.