代理产线

EMCP (eMMC + LPDDR2/3)

 2016-08-17

【基本数据】

【产品特性】

• Separate eMMC™ and LPDDR2/3 interfaces
• Operating temperature: –25°C to +85°C / Storage temperature: –55°C to +125°C
• Package size 162/221 ball FBGA (11.5 x 13.0 x (0.9mm ± 0.1mm, Max 1.0mm) )
(Note: eMMC + LPDDR2 is 162 ball, eMMC + LPDDR3 is 221 ball)
< eMMC™ - NAND>
• eMMC™ 5.0 interface (Compliant with eMMC™ Specification Ver.4.4, 4.41,4.5&5.0)
• NAND Density & Attribute: 8GB、MLC (2 bit/cell) / TLC (3 bit/cell)
• Bus mode
- High-speed eMMC™ protocol
- Provide variable clock frequencies of 0-200MHz.
- Ten-wire bus (clock, 1 bit command, 8 bit data bus) and a hardware reset.
• Operating voltage range : VCCQ = 1.8 V/3.3 V, VCC = 3.3 V

• Density: 4Gbits x2
• Organization
- × 16 bits: 32M words × 16 bits × 8 banks (LPDDR3)
- × 32 bits: 16M words × 32 bits × 8 banks (LPDDR2)
- 2 pieces of 4Gb in one package(For 8Gb case)
- Row Address: R0 ~ R13 - Column Address: C0 ~ C9 (x32 bits )
• Power supply : VDD1 = 1.70V to 1.95V, VDD2, VDDQ = 1.14V to 1.30V
• LPDDR3 data rate: 1600Mbps max. (RL = 12)
LPDDR2 data rate: 1066Mbps max. (RL = 8)
• Quality - Lead-free (RoHS compliant) and Halogen-free
• eMCP is a Multi-Chip Package Memory which combines eMMC™ and Low Power DDR2/3 synchronous dynamic RAM.
• The eMMC™ part is an embedded flash memory storage solution with MultiMediaCard interface (eMMC™)
• Low power consumption
• JEDEC LPDDR2-S4B /JEDEC LPDDR3 compliance
• Per Bank Refresh
• Partial Array Self-Refresh (PASR) - Bank Masking - Segment Masking
• Auto Temperature Compensated Self-Refresh
• Deep power-down mode
• Double-data-rate architecture; two data transfers per one clock cycle
• The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture
• Data mask (DM) for write data
• Burst termination by burst stop command

【产品应用】

eMCP产品主要应用于智能型手机、平板计算机等移动设备产品,也用在穿戴式装置,如智能手表、智慧眼镜,或是GPS导航装置的理想储存解决替代方案。

【文字介绍】

金士顿eMCP则是将eMMC以及LPDDR封装在一起,减小体积的同时还减少了电路链接设计,eMMC是采用A19nm MLC NAND Flash,符合JEDEC eMMC 5.0规范标准,LPDDR则是采用LPDDR2/3, 尺寸大小皆为11.5x13.0x (0.9mm ± 0.1mm, Max 1.0mm),采用FBGA封装162/221 ball (162 ball is eMMC + LPDDR2, 221 ball is eMMC + LPDDR3)。