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MT41K256M16LY-107:N DDR3 Componet

 2016-01-06

【产品特性】

VDD = VDDQ = 1.35V (1.283–1.45V)
Differential bidirectional data strobe
8n-bit prefetch architecture
‧Differential clock inputs (CK, CK#)
‧Nominal and dynamic on-die termination (ODT)
‧Programmable CAS (READ) latency (CL)
‧Programmable posted CAS additive latency (AL)

【产品应用】

STB ,TV , Auto infortainment , Mid

【文字介绍】

DDR3 SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write operation for the DDR3 SDRAM effectively consists of a single 8n-bit-wide, four-clockcycle,data transfer at the internal DRAM core and eight corresponding n-bit-wide, onehalf- clock-cycle data transfers at the I/O pins